Adoption of 56G and 112G SerDes in data center switch SoC platforms are enabling significant increases in bandwidth, however as these data rates and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get cut in half, presenting new design challenges.? We offer the largest portfolio of timing products for 100G/400G switch platforms, addressing both synchronous and asynchronous architectures with our sub-100 fs families of Si54x oscillators, Si5391 clock generator, Si5395/4/2 jitter attenuators, and IEEE 1588 networking synchronizer hardware and software solutions. ?
Selecting a timing solution for switch designs starts with an outline of all the reference clocks, performance levels, and associated timing features needed within the design, commonly known as a clock tree.? The frequencies, output formats, and associated RMS phase jitter requirements are typically outlined in the switch SoC and PHY datasheets. We recommend considering the following when outlining your clock tree and selecting the ideal timing solution to implement:
Timing Architecture:??Before outlining a detailed clock tree, the first step is to define whether the switch design is asynchronous (or free-running), synchronous, and whether or not IEEE 1588 PTP synchronization support is needed.? Synchronous designs need to lock to an incoming clock from another source and will require the use of a jitter attenuator to filter jitter from the incoming reference clock prior to frequency generation.? Alternatively, asynchronous designs generate all frequencies locally, typically using clock generators or oscillators.
Performance:?RMS phase jitter is the most important parameter to review before selecting a timing solution.? As data rate and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get twice as rigorous, oftentimes cutting system jitter budgets in half.? The latest generation of switch SoCs and PHYs for 400G switches incorporate 56G/112G SerDes, which require reference clocks with less than 150 fs of RMS phase jitter, whereas lower 40G/100G bandwidth designs use 28G SerDes with 300 fs RMS phase jitter requirements on the reference clocks.? We recommend summarizing your clock tree in order of importance, listing the clocks with the most stringent RMS phase jitter requirements at the top.? Silicon Labs’ oscillator, clock generators, and jitter attenuators?are segmented by the RMS phase jitter performance level, making it easy to select the right device matching your specific requirements.
Frequency Flexibility: Data center switch designs commonly need a combination of different frequencies, at different output format levels, at different output voltages.? Silicon Labs' patented DSPLL and MultiSynth technologies provide a high degree of clock synthesis capability with 0ppm synthesis error on both integer and fractional related output frequencies on up to 12 outputs while minimizing external components and delivering industry-best jitter performance.? ?Our Si5332/Si5391 clock generators and Si5395 jitter attenuator are capable of supplying 312.5M, 156.25M, 100M, 50M, and 25M output clocks at the same time, satisfying entire data center switch clock trees in single-IC solutions.
Feature Set and Integration:?Silicon Labs’ timing solutions come equipped with many features that can further optimize and simplify your switch design, such as hitless switching, loss of signal, spread spectrum for EMI reduction, frequency selection capability, output enable control, multi-profile selection, and integrated crystal reference source.? We know that jitter performance is of the highest importance, so our products include on-chip LDOs on all power pins, resulting in industry best PSNR performance.? Suppressing external power supply and board-level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.
Customization:?Our ClockBuilder Pro software tool?guides you through an easy, step-by-step process to generate a clock generator or jitter attenuator configuration file specific to your clock tree requirements.? When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use.? Part number generation for our Si54x Ultra Series Oscillators can be configured directly on our website.
IEEE 1588:??With data centers becoming an increasingly important element in our communications infrastructure, IEEE 1588 PTP will soon become standard within data center network switching equipment, just as it has in 5G wireless infrastructure and core/metro routing.? Silicon Labs offers a new approach to PTP timing supporting G.8262, G.8262.1, and G.8273.2 T-BC Class C and Class D.? We offer a complete portfolio of network synchronizers, AccuTime software, and module solutions ideally suited for distributed timing architectures within data center switching applications.
Availability: Sourcing components on short notice to meet prototype or production builds can be challenging. ?Our solutions-oriented approach to developing flexible, programmable silicon that can be easily configured using ClockBuilder Pro allows for seamless integration within our manufacturing flow to support pre-programmed samples in less than 2 weeks, and production quantities in as little as 4 weeks.? Our field programmer also provides the capability to program blank devices on a moment’s notice, or re-configure a device using I2C.?